Push-pull resistive random access memory (ReRAM) cells, such as the ones disclosed in U.S. Pat. No. 8,415,650, are attractive for use in configuration memory for configurable logic integrated circuits such as field programmable gate arrays (FPGAs).
When designing circuits using deep sub-micron (14 nM and beyond) transistors, any change in transistor pitch forces designers to use a large transition region to allow photolithographic production of the pattern. This transition region can range from 0.2 um to 1 um or more and can be a significant disadvantage in designing a configurable logic integrated circuit employing ReRAM push-pull configuration memory cell circuits that has a compact efficient layout.
An FPGA requires logic, routing switches, and programming transistors to be intermingled. To eliminate the transition region which is required by photolithography processing requirements, all the above listed devices must have the same pitch, including channel length pitch. Normally this requirement is not compatible with devices that are operated at different voltages.
For ReRAM memory cells, the transistor devices used to program them will be subjected to higher drain and gate biases, and will switch at a higher gate bias during programming and operation as compared to other transistors employed in the integrated circuit.
Therefore, there is a need for a design for ReRAM configuration memory cells which is not associated with these disadvantages. An objective of the present invention is to provide ReRAM push-pull configuration memory cell circuits that eliminate this transition region.